https://github.com/luickk/zig-gicv2

arm generic interrupt controller v2 for cortex a57 kernel
https://github.com/luickk/zig-gicv2

aarch64 arm bare-metal freestanding kernel zig

Last synced: about 10 hours ago
JSON representation

arm generic interrupt controller v2 for cortex a57 kernel

• Host: GitHub
• URL: https://github.com/luickk/zig-gicv2
• Owner: luickk
• Created: 2022-07-20T08:12:35.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2022-12-08T09:28:59.000Z (almost 2 years ago)
• Last Synced: 2023-03-07T14:54:26.338Z (over 1 year ago)
• Topics: aarch64, arm, bare-metal, freestanding, kernel, zig
• Language: Zig
• Homepage:
• Size: 49.8 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
# Zig gicv2

This repository contains a basic generic interrupt controller for aarch64, specifically the a57 (tested with qemu). gicv2 docs can be found [here](https://developer.arm.com/documentation/ihi0069/latest).

## Example Arm Timer Interrupt

```zig

	// disabling & clearing all pending irqs, setting all irqs to lowest priority, setting target core to 0

	// enabling gicc and gicd

	try Gic.init();

	// setting timer irq to edge-triggered(0x2)

	try Gic.Gicd.gicdConfig(Gic.InterruptIds.non_secure_physical_timer, 0x2);

	// setting timer irq to highest priority 0

	try Gic.Gicd.gicdSetPriority(Gic.InterruptIds.non_secure_physical_timer, 0);

	// setting target to core 0 (1 for the register write)

	try Gic.Gicd.gicdSetTarget(Gic.InterruptIds.non_secure_physical_timer, 1);

	// clearing if pending so that new vector table call can be invoked

	try Gic.Gicd.gicdClearPending(Gic.InterruptIds.non_secure_physical_timer);

	// finally enabling timer interrupt

	try Gic.Gicd.gicdEnableInt(Gic.InterruptIds.non_secure_physical_timer);

```