https://github.com/luk3sky/building-a-processor---project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
https://github.com/luk3sky/building-a-processor---project
alu hdl processor-architecture verilog-hdl verilog-project
Last synced: 7 months ago
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Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
- Host: GitHub
- URL: https://github.com/luk3sky/building-a-processor---project
- Owner: luk3Sky
- Created: 2018-12-17T10:35:05.000Z (almost 7 years ago)
- Default Branch: master
- Last Pushed: 2019-01-28T07:38:57.000Z (over 6 years ago)
- Last Synced: 2025-01-26T11:11:10.926Z (9 months ago)
- Topics: alu, hdl, processor-architecture, verilog-hdl, verilog-project
- Language: Verilog
- Size: 880 KB
- Stars: 7
- Watchers: 1
- Forks: 1
- Open Issues: 0
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Metadata Files: