https://github.com/madhurjain/pipelined-radix-2-sdf-fft

Variable Length Pipelined Radix-2 SDF (R2SDF) FFT Implementation in VHDL
https://github.com/madhurjain/pipelined-radix-2-sdf-fft

Last synced: 2 months ago
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Variable Length Pipelined Radix-2 SDF (R2SDF) FFT Implementation in VHDL

Host: GitHub
URL: https://github.com/madhurjain/pipelined-radix-2-sdf-fft
Owner: madhurjain
Created: 2016-05-16T06:33:52.000Z (almost 9 years ago)
Default Branch: master
Last Pushed: 2016-05-16T06:40:15.000Z (almost 9 years ago)
Last Synced: 2025-01-01T22:43:36.419Z (4 months ago)
Language: VHDL
Size: 51.8 KB
Stars: 4
Watchers: 2
Forks: 3
Open Issues: 1
Metadata Files:
- Readme: README.md

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README

        Pipelined Radix-2 Singlepath Delay Feedback (R2SDF) FFT Implementation in VHDL

===============================================================================

Implemented and simulated using Xilinx Vivado 2015.4. Uses `ieee_proposed` library for fixed point arithmetic.

![Simulation Waveform](./output.png)