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https://github.com/magic3007/riscv-simulator
✨ A Simple RISCV ISA Simulator that supports RV64I Base Instruction Set and RV64M Standard Extension, and can run in both single-instruction mode and pipeline mode.
https://github.com/magic3007/riscv-simulator
riscv
Last synced: about 21 hours ago
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✨ A Simple RISCV ISA Simulator that supports RV64I Base Instruction Set and RV64M Standard Extension, and can run in both single-instruction mode and pipeline mode.
- Host: GitHub
- URL: https://github.com/magic3007/riscv-simulator
- Owner: magic3007
- Created: 2020-03-09T07:19:08.000Z (almost 5 years ago)
- Default Branch: master
- Last Pushed: 2020-05-13T13:37:26.000Z (over 4 years ago)
- Last Synced: 2024-06-21T16:55:30.876Z (7 months ago)
- Topics: riscv
- Language: Go
- Homepage:
- Size: 1.59 MB
- Stars: 4
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.assets/pipeline-demo.gif