https://github.com/mahdisafsafi/opcodesdb

x86-64 | ARM (AArch32/AArch64/THUMB) full instruction set.
https://github.com/mahdisafsafi/opcodesdb

aarch32 aarch64 arm isa opcodes thumb x64 x86

Last synced: about 1 month ago
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x86-64 | ARM (AArch32/AArch64/THUMB) full instruction set.

• Host: GitHub
• URL: https://github.com/mahdisafsafi/opcodesdb
• Owner: MahdiSafsafi
• License: mit
• Created: 2017-01-09T14:57:33.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2020-03-15T16:31:32.000Z (almost 5 years ago)
• Last Synced: 2023-02-27T07:56:09.290Z (almost 2 years ago)
• Topics: aarch32, aarch64, arm, isa, opcodes, thumb, x64, x86
• Language: Perl
• Homepage:
• Size: 1.32 MB
• Stars: 58
• Watchers: 10
• Forks: 13
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# opcodesDB:

opcodesDB is a CPU low level environment representation (registers, flags, instructions, ...).  Data are listed in a packed dynamic structure which can be unpacked by a parser at any time.

This project is a fruit of many years of development and a lot of attempts ([Parsable-Instructions](https://github.com/MahdiSafsafi/Parsable-Instructions), [asmdb](https://github.com/MahdiSafsafi/asmdb)) to standardize CPU environment.

Currently, it supports the following architectures:

- x86    : with all its extensions : FPU, MMX, SSE, FMA, AVX, AVX512. also it supports xeon instructions(KNC, KNL, ...).

- aarch32: arm and thumb instructions(ARMv8+).

- aarch64: ARMv8+ and SVE extension.

# Whats new in version 3 ?

- added aarch32 support.

- added aarch64 support.

- added xeon instruction set.

- improved x86 instructions definition.

# How to use it ?

you just need to run **x86.pl**, **aarch32.pl**, **aarch64.pl** and for each architecture, opcodesDB will generate a very big json file that contains all the architecture environment(instructions, registers, enums, tables, ...). All generated files (**x86.json**, **aarch32.json**, **aarch64.json**) are stored in the json folder.