https://github.com/mahdizynali/verilog-digital-circuit-codes
simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
https://github.com/mahdizynali/verilog-digital-circuit-codes
arithmatic fulladder fullsubtractor halfadder halfsubtractor logic multiplexer mux shift-left shift-register shift-right verilog verilog-code
Last synced: 3 months ago
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simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
- Host: GitHub
- URL: https://github.com/mahdizynali/verilog-digital-circuit-codes
- Owner: mahdizynali
- Created: 2023-06-06T14:37:52.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2023-06-09T06:24:45.000Z (almost 2 years ago)
- Last Synced: 2025-01-07T17:45:09.727Z (5 months ago)
- Topics: arithmatic, fulladder, fullsubtractor, halfadder, halfsubtractor, logic, multiplexer, mux, shift-left, shift-register, shift-right, verilog, verilog-code
- Language: Verilog
- Homepage:
- Size: 13.7 KB
- Stars: 8
- Watchers: 1
- Forks: 1
- Open Issues: 0
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Metadata Files: