https://github.com/mahdizynali/verilog-digital-circuit-codes

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)
https://github.com/mahdizynali/verilog-digital-circuit-codes

arithmatic fulladder fullsubtractor halfadder halfsubtractor logic multiplexer mux shift-left shift-register shift-right verilog verilog-code

Last synced: about 1 month ago
JSON representation

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

• Host: GitHub
• URL: https://github.com/mahdizynali/verilog-digital-circuit-codes
• Owner: mahdizynali
• Created: 2023-06-06T14:37:52.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2023-06-09T06:24:45.000Z (over 1 year ago)
• Last Synced: 2024-11-10T13:17:00.450Z (3 months ago)
• Topics: arithmatic, fulladder, fullsubtractor, halfadder, halfsubtractor, logic, multiplexer, mux, shift-left, shift-register, shift-right, verilog, verilog-code
• Language: Verilog
• Homepage:
• Size: 13.7 KB
• Stars: 8
• Watchers: 1
• Forks: 1
• Open Issues: 0

Awesome Lists containing this project