https://github.com/majekdor/cache-simulator

Simple cache simulator designed to simulate L1 with potential L2 backing.
https://github.com/majekdor/cache-simulator

cache rust simulator

Last synced: 26 days ago
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Simple cache simulator designed to simulate L1 with potential L2 backing.

• Host: GitHub
• URL: https://github.com/majekdor/cache-simulator
• Owner: Majekdor
• Created: 2022-10-14T02:55:47.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2022-10-14T02:58:49.000Z (over 2 years ago)
• Last Synced: 2024-11-08T18:52:08.588Z (3 months ago)
• Topics: cache, rust, simulator
• Language: Rust
• Homepage:
• Size: 120 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# cache-simulator

Simple cache simulator designed to simulate L1 with potential L2 backing.

This simulator was originally written in C++ for ECE 463 (Microprocessor Architecture). I rewrote it in Rust to get more practice with the language and compare efficiency with C++.

The caches used LRU replacement policy and are WBWA.