https://github.com/malisha4065/risc-processor

32 bit risc processor designed using verilog
https://github.com/malisha4065/risc-processor

hdl modelsim verilog

Last synced: 5 months ago
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32 bit risc processor designed using verilog

• Host: GitHub
• URL: https://github.com/malisha4065/risc-processor
• Owner: Malisha4065
• Created: 2024-03-17T08:41:09.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2024-03-23T15:26:45.000Z (over 2 years ago)
• Last Synced: 2025-04-14T03:38:40.700Z (about 1 year ago)
• Topics: hdl, modelsim, verilog
• Language: Verilog
• Homepage:
• Size: 1.04 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# 32-Bit RISC Processor using Verilog

This project presents a 32-bit RISC processor with a memory controller, completed as a 3rd-year group project for the HDL module at the University of Ruhuna, SL. The processor features a streamlined architecture for faster execution times, utilizing Verilog HDL for implementation and ModelSim for simulation.

## Project Overview

The project aimed to design and implement a Reduced Instruction Set Computing (RISC) processor with a memory controller. The processor is equipped with 15 essential instructions covering arithmetic, logical, data transfer, and control operations. Key components include the Control Unit (CU), Arithmetic and Logic Unit (ALU), Accumulator, Program Counter (PC), Instruction Register (IR), Memory Module, and additional logic blocks.

## Repository Contents

- `Project_Report.pdf`: Detailed project report.

- `Verilog_Implementation/`: Verilog HDL code for each module of the RISC processor.

  - `Accumulator.v`

  - `ALU.v`

  - `Buffer.v`

  - `Control_Unit.v`

  - `Instruction_Register.v`

  - `Memory_Module.v`

  - `MUX.v`

  - `Program_Counter.v`

  - `Processor.v`

- `Testing_and_Verification/`: Test bench results for each module.

##  Architecture of the RISC Processor

 ![Project Image](./ArchitectureOfProcessor.png)

## How to Use

1. Clone the repository:

`git clone https://github.com/Malisha4065/RISC-Processor.git`

2. Navigate to the `Verilog_Implementation/` directory to access the Verilog code for each module.

3. Open the Verilog files in a suitable development environment (e.g., Modelslim Vivado, Quartus Prime) for synthesis and simulation.

4. Explore the `Project_Report.pdf` for a comprehensive overview of the project, including design rationale, methodology, and results.

## Contributors

- Dushmin Malisha

- Sahan Lelwala

- Sanjula Lakpahana