https://github.com/manpen/embedded-logic-analyzer

A simple embedded logic analyzer intended for debugging of FPGA designs
https://github.com/manpen/embedded-logic-analyzer

Last synced: 2 months ago
JSON representation

A simple embedded logic analyzer intended for debugging of FPGA designs

• Host: GitHub
• URL: https://github.com/manpen/embedded-logic-analyzer
• Owner: manpen
• Created: 2012-02-20T21:11:56.000Z (over 13 years ago)
• Default Branch: master
• Last Pushed: 2013-05-21T19:12:45.000Z (about 12 years ago)
• Last Synced: 2025-04-13T07:15:10.718Z (2 months ago)
• Language: VHDL
• Homepage:
• Size: 1.35 MB
• Stars: 1
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README

Awesome Lists containing this project

README

        
This project is under development and not intended

for public use yet. While the hardware should work quite

well with the Xilinx Toolchain (tested with Spartan 3

and Virtex 4), the software client is rarely tested.

There is no explicit english documentation yet, but each

vhd-file contains a brief introduction, and the c++ codes

include doxygen annotations. Additionally in the doc-folder

there's an example showing how-to embed the core.