https://github.com/mantisclone/ece_cs_552_vertically_designed_single_cycle_processor

This repository contains responses to the homeworks and project prompts for the Spring 2014 semester of ECE/CS 552 Introduction to Computer Architecture class.
https://github.com/mantisclone/ece_cs_552_vertically_designed_single_cycle_processor

Last synced: 26 days ago
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This repository contains responses to the homeworks and project prompts for the Spring 2014 semester of ECE/CS 552 Introduction to Computer Architecture class.

• Host: GitHub
• URL: https://github.com/mantisclone/ece_cs_552_vertically_designed_single_cycle_processor
• Owner: MantisClone
• Created: 2014-03-04T21:18:36.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2014-05-09T02:59:27.000Z (over 10 years ago)
• Last Synced: 2024-04-14T10:29:29.660Z (7 months ago)
• Language: Verilog
• Homepage:
• Size: 2.03 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
WARNING!!! UNTIL STATED OTHERWISE, THE TOP LEVEL OF THIS REPO IS OUT OF DATE.  THE CURRENT WORK BEING DONE IS IN "ThePipeliners" FOLDER.

ECE/CS 552 Vertically Designed Pipelined Processor


  This repository contains responses to the homeworks and project prompts for the Spring 2014 semester of ECE/CS 552        Introduction to Computer Architecture Class.  

  

Contributors


  David Mateo


  R. Scott Carson

  

Contents


Top Level Module

This folder contains the top level module, build script, and test bench.


cpu.v


cpu_tb.v


build.sh


5 Pipeline Stages

The following folders contain the files relating to the 5 stages of the Single Cycle Processor.


IF - Instruction Fetch


ID - Instruction Decode


EX - Execute


MEM - Memory


WB - Write Back


Other

This folder contains files used for purposes other than the main pipelined processor project.  This includes files for homework questions.