https://github.com/manuelblancovalentin/alu32_verilog

https://github.com/manuelblancovalentin/alu32_verilog

Last synced: 25 days ago
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• Host: GitHub
• URL: https://github.com/manuelblancovalentin/alu32_verilog
• Owner: manuelblancovalentin
• Created: 2020-11-12T04:41:05.000Z (about 4 years ago)
• Default Branch: main
• Last Pushed: 2020-11-12T04:44:17.000Z (about 4 years ago)
• Last Synced: 2024-11-08T10:34:31.206Z (3 months ago)
• Language: Verilog
• Size: 26.6 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README

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README

        
%%%%%%%%%% FILE CREATED BY MANUEL BLANCO VALENTIN

%%%%%%%%%%

PLEASE NOTICE THAT ALL THE INFORMATION SHOWN IN HERE IS EXPLICITELY DETAILED IN THE PDF REPORT SUBMITTED.

THIS ZIP CONTAINS the following content:

- README -> This readme file.

- genus_synthesis.tcl -> This is a tcl file used to run all the instructions for synthesis with genus at once, without having to type manually everything every time I synthesized. 

- Makefile -> This is a makefile used to call the clean, synthesize (genus) and verification (xcelium) using a single command-line, to avoid having to type repetitively the same command over and over.

+ src -> This folder contains all the source code used for the project.

	+ cad -> This folder contains the open-source verilog libraries that should be used to implement our design (NangateOpenCell...). I put them in here so 				that my code is totally standalone and does not depend on any specific machine/cluster.

	+ eecs361lib_alu_Verilog -> This folder contains the source verilog files that were given to us by the professor via CANVAS. All my implementations use 				these codes. I did not use all of them (I ignored the "*_n.v" versions such as "and_gate_n.v")

	- ALU_32.sdc -> Timing constraints file for synthesis. I just renamed the file specified in the GENUS tutorial and put it in here, again, so that my code 				is fully standalone.

	- ALU_32.v, arithmetic_unit_32.v, comparison_unit_32.v, full_adder.v, full_fast_adder.v, logic_unit_32.v, mux2to1_32.v, mux4to1_32.v, nor_gate_32to1.v and 	

				shift_unit_32.v -> These are ALL my implementations and codes. I implemented these codes from scratch and tried to leave them as commented as possible. They were implemented using the libraries found at "eecs361lib_alu_Verilog" folder.

	- ALU_tb.v -> This is my testbench. I implemented this testbench from scratch too. I use it for both the "original" design and the netlist generated by 	

				genus after synthesis. 

+ Synthesis -> This folder contains the results of the synthesis process by genus (netlist, area/timing reports, .cmd, .log, etc.)

+ Verification -> This folder contains all the results of the verification/simulation of my testbench for both cases (original design and synthesized netlist)

	+ run-post-hls -> This folder contains the result of the verification for the original design (I mean, BEFORE SYNTHESIS). 

	+ run-post-syn -> The same, for the verification results for the netlist generated by genus (POST-SYNTHESIS).

	- waves.tcl -> A tcl script that can be imported to xcelium to obtain the Waveform screen disposition that I used for the screenshots that appear in my PDF 

					report.