https://github.com/marceldobehere/goofy-cpu-verilog

https://github.com/marceldobehere/goofy-cpu-verilog

cpu cpu-simulator goofy goofy-cpu sim verilog

Last synced: 2 months ago
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• Host: GitHub
• URL: https://github.com/marceldobehere/goofy-cpu-verilog
• Owner: marceldobehere
• License: agpl-3.0
• Created: 2024-04-01T23:00:12.000Z (about 2 years ago)
• Default Branch: master
• Last Pushed: 2024-05-08T21:16:46.000Z (about 2 years ago)
• Last Synced: 2025-10-19T08:38:56.129Z (8 months ago)
• Topics: cpu, cpu-simulator, goofy, goofy-cpu, sim, verilog
• Language: Verilog
• Homepage:
• Size: 209 KB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Goofy CPU (Verilog)

A verilog implementation of my [goofy cpu](https://github.com/marceldobehere/goofy-cpu)!

It was mainly made to learn and try out verilog!

It has not been tested with a lot of stuff but for the test program it works which is cool.

Currently I am not working on this or the goofy cpu as I am working on other projects.

I might get back to this or to cpu dev in general though!

## Screenshots

![Some logs from the cpu running the adder program](./images/logs.png)

![The ALU signals from the cpu running the adder program](./images/signals.png)