https://github.com/martinkindall/risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
https://github.com/martinkindall/risc-v-single-cycle
basys3 basys3-fpga riscv riscv-assembly riscv32 rv32i single-cycle-processor systemverilog
Last synced: 2 months ago
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A Single Cycle Risc-V 32 bit CPU
- Host: GitHub
- URL: https://github.com/martinkindall/risc-v-single-cycle
- Owner: martinKindall
- Created: 2022-12-21T23:11:55.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-02-11T10:34:39.000Z (over 2 years ago)
- Last Synced: 2023-03-04T19:40:25.746Z (about 2 years ago)
- Topics: basys3, basys3-fpga, riscv, riscv-assembly, riscv32, rv32i, single-cycle-processor, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 36.1 KB
- Stars: 3
- Watchers: 2
- Forks: 1
- Open Issues: 0