https://github.com/masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
https://github.com/masc-ucsc/livehd

asic fpga hdl lgraph live simulation synthesis

Last synced: about 1 month ago
JSON representation

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

• Host: GitHub
• URL: https://github.com/masc-ucsc/livehd
• Owner: masc-ucsc
• License: other
• Created: 2018-04-23T20:44:49.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2024-04-13T13:57:10.000Z (about 1 year ago)
• Last Synced: 2024-04-13T21:02:47.950Z (about 1 year ago)
• Topics: asic, fpga, hdl, lgraph, live, simulation, synthesis
• Language: Verilog
• Homepage:
• Size: 120 MB
• Stars: 196
• Watchers: 28
• Forks: 46
• Open Issues: 11
• Metadata Files:
  • Readme: README.md
  • Contributing: docs/CONTRIBUTING.md
  • License: LICENSE
  • Code of conduct: docs/CODE_OF_CONDUCT.md
  • Citation: CITATION.cff

Awesome Lists containing this project

• awesome-opensource-hardware - livehd