https://github.com/masterdezign/clash-fifo-test
https://github.com/masterdezign/clash-fifo-test
Last synced: 6 months ago
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- Host: GitHub
- URL: https://github.com/masterdezign/clash-fifo-test
- Owner: masterdezign
- Created: 2015-06-15T15:41:47.000Z (about 11 years ago)
- Default Branch: master
- Last Pushed: 2015-06-18T16:19:14.000Z (about 11 years ago)
- Last Synced: 2025-07-04T19:40:10.414Z (about 1 year ago)
- Language: VHDL
- Size: 156 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Fifo delay line in CLaSH
This FIFO delay line design features [AD1](http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD1)
and [DA4](http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-DA4) components
along with [Nexys4](http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS4) board running @50MHz.
AD1 sampling rate - FIFO data flow rate - DA4 output rate equal 1 megasample per second.