https://github.com/matteoldani/progetto-reti-logiche-2021
Implementation on FPGA of a simplified equalization algorithm for gray scale images
https://github.com/matteoldani/progetto-reti-logiche-2021
Last synced: 3 months ago
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Implementation on FPGA of a simplified equalization algorithm for gray scale images
- Host: GitHub
- URL: https://github.com/matteoldani/progetto-reti-logiche-2021
- Owner: matteoldani
- Created: 2021-03-08T11:57:29.000Z (over 4 years ago)
- Default Branch: master
- Last Pushed: 2022-02-02T15:59:30.000Z (over 3 years ago)
- Last Synced: 2025-01-21T01:15:03.218Z (5 months ago)
- Language: VHDL
- Size: 22.8 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Digital Systems Final Project
Implementation of a simple histogram equalization algorithm on FPGA through VHDL. More information can be found in the report.
## Authors
[@MargheritaMusumeci](https://github.com/MargheritaMusumeci) \
[@matteoldani](https://github.com/matteoldani)