https://github.com/mattvenn/axi-lite-formal

https://github.com/mattvenn/axi-lite-formal

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/mattvenn/axi-lite-formal
• Owner: mattvenn
• Created: 2019-05-18T21:53:25.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2019-05-23T12:58:21.000Z (almost 6 years ago)
• Last Synced: 2025-04-01T18:09:53.802Z (about 2 months ago)
• Language: Verilog
• Size: 25.4 KB
• Stars: 3
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
This is the blog post: http://zipcpu.com/formal/2018/12/28/axilite.html

Dan got a demo axi core from Vivado, pictures in this post (but for axi full)

http://zipcpu.com/formal/2019/05/13/axifull.html

Here is the demo axi lite core as generated by Vivado:

https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/xlnxdemo.v

Dan's axi-lite slave formal properties:

https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v

sby file:

https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/xlnxdemo.sby

gtkw file:

https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/xlnxdemo.gtkw