https://github.com/mattvenn/flipflop_demo

Flip flop setup, hold & metastability explorer tool
https://github.com/mattvenn/flipflop_demo

flip-flop metastability ngspice simulation sky130

Last synced: 20 days ago
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Flip flop setup, hold & metastability explorer tool

• Host: GitHub
• URL: https://github.com/mattvenn/flipflop_demo
• Owner: mattvenn
• License: apache-2.0
• Created: 2022-01-14T16:58:51.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-10-28T11:39:02.000Z (about 2 years ago)
• Last Synced: 2024-01-29T08:10:50.916Z (10 months ago)
• Topics: flip-flop, metastability, ngspice, simulation, sky130
• Language: Jupyter Notebook
• Homepage: https://zerotoasiccourse.com
• Size: 34.1 MB
• Stars: 27
• Watchers: 5
• Forks: 4
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

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README

        
# Interactive flip flop simulation

Made for a video about flip flops: https://www.youtube.com/watch?v=5PRuPVIjEcs

For the [Zero to ASIC course](https://ZeroToASICcourse.com)

![screenshot](screenshot.png)

## To play with bundled data set from SKY130 df transmission gate flip flop

    git clone https://github.com/mattvenn/flipflop_demo

    cd flipflop_demo/spice

    tar xf csv.tar.bz2

    ./wave.py

You will probably need to install the [requirements](spice/requirements.txt)

    pip3 install -r spice/requirements.txt

## If you want to build the GDS of the design

After install of openlane/pdk etc, copy this directory to $OPENLANE_ROOT/designs. Then:

    cd $OPENLANE_ROOT

    make mount

    ./flow.tcl -design flipflop_demo

## Create the dataset yourself

This will simulate moving a data pulse through the setup and hold times of a d type flop.

    make setup

    make sim

![schematic](schematic/tgff_with_clock.png)

Takes about 8 mins on my laptop.

[Schematic generated with schemdraw](schematic/tg_ff.py) with thanks to Proppy.

## Fun facts

The flip flop is one of the largest and most complex [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/). Here's the [GDS](https://www.zerotoasiccourse.com/terminology/gds2/) layout:

![gds](gds.png)

* 26 fets, 13 CMOS pairs

* 7 inverters

* 2 tristate inverters

* 2 transmission gates