https://github.com/mattvenn/formal_timer

Project 3.1 Formal timer
https://github.com/mattvenn/formal_timer

formal-verification sby yosyshq

Last synced: 9 months ago
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Project 3.1 Formal timer

• Host: GitHub
• URL: https://github.com/mattvenn/formal_timer
• Owner: mattvenn
• License: apache-2.0
• Created: 2021-01-17T19:24:04.000Z (almost 5 years ago)
• Default Branch: main
• Last Pushed: 2022-05-24T11:11:44.000Z (over 3 years ago)
• Last Synced: 2025-04-01T18:09:56.610Z (9 months ago)
• Topics: formal-verification, sby, yosyshq
• Language: Verilog
• Homepage: https://zerotoasiccourse.com
• Size: 6.84 KB
• Stars: 3
• Watchers: 2
• Forks: 5
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

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README

          
# Formal Timer

This repository is a template for project 3.1 that takes you through:

* Writing a cover statement to show the timer starting and ending.

* Writing some assertions to prove the timer works as designed.

# License

This repo is part of the [Zero to ASIC course](https://zerotoasiccourse.com) and licensed with [Apache 2](LICENSE).

# Resources

* SBY docs https://symbiyosys.readthedocs.io/en/latest/index.html

* Getting started with Formal Verification youtube course: https://www.youtube.com/playlist?list=PLX1FD-Xa88fbMhT-tTe67O2gz_UwEjz9-