https://github.com/mattvenn/fpga-lvds-ddr

https://github.com/mattvenn/fpga-lvds-ddr

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/mattvenn/fpga-lvds-ddr
• Owner: mattvenn
• Created: 2017-01-10T14:44:01.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-01-10T14:59:59.000Z (over 8 years ago)
• Last Synced: 2025-04-01T18:09:56.601Z (about 2 months ago)
• Language: Verilog
• Size: 6.84 KB
• Stars: 5
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# differential DDR

using [Lattice ICE40HX](http://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx#_21E33C7EC0BD48AA80FE384ED73CC895)

[The IceStorm flow (Yosys, Arachne-pnr, and IceStorm) is a fully open source Verilog-to-Bitstream flow for iCE40 FPGAs](http://www.clifford.at/icestorm/)

![ddr](ddr.png)

* Trace 3: system clock 12MHz

* Trace 2: DDR clock from PLL 25Mhz

* Trace 1: DDR differential positive

* Trace 0: DDR differential negative

# docs

PLL and DDR are setup with SB_IO and SB_PLL primitives:

* [PLL details](http://www.latticesemi.com/view_document?document_id=47778)

* [DDR details](http://www.latticesemi.com/view_document?document_id=47960)