https://github.com/mattvenn/fpga-sram
mystorm sram test
https://github.com/mattvenn/fpga-sram
Last synced: about 2 months ago
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mystorm sram test
- Host: GitHub
- URL: https://github.com/mattvenn/fpga-sram
- Owner: mattvenn
- Created: 2017-03-11T17:41:12.000Z (about 8 years ago)
- Default Branch: master
- Last Pushed: 2017-09-12T11:42:19.000Z (over 7 years ago)
- Last Synced: 2025-04-01T18:09:56.717Z (about 2 months ago)
- Language: Verilog
- Size: 526 KB
- Stars: 27
- Watchers: 3
- Forks: 3
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# SRAM on the mystorm blackice
[mystorm](https://mystorm.uk/) blackice has 0.5MByte SRAM on the back of the board
[datasheet for SRAM](ram.pdf)
[mystorm blackice schematic](mystorm.pdf)
From datasheet: ISSI IS62WV25616DALL and IS62/65WV25616DBLL are high-speed, low power, 4M bit SRAMs organized as 256K words by 16 bits.
## verilog
* extremely simple test of the SRAM
* state machine for read and write
* everything done in 1 cycle as 1 cycle at 12MHz is slower than max read/write
time of the SRAM.
[sram.v](sram.v)
## current status
* working at 12MHz system clock
* test reads then writes to first 2^16 words
* data written is the current address
* bits 14:11 of the data is shown on the boards's 4 leds
* [boring test video](https://goo.gl/photos/QZVVtneaXWpWAp4N6)
## testbench
[sram_tb.v](sram_tb.v)
## problems
2 pins on the data bus collide with pins of the PLLs. When the PLL is
activated, those pins can no longer be inout, they must be either in or out.
[More details here](https://github.com/cseed/arachne-pnr/issues/64#issuecomment-310877601)