https://github.com/mattvenn/frequency_counter

Project 2.2 Frequency counter
https://github.com/mattvenn/frequency_counter

asic hdl verilog

Last synced: 7 days ago
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Project 2.2 Frequency counter

• Host: GitHub
• URL: https://github.com/mattvenn/frequency_counter
• Owner: mattvenn
• License: apache-2.0
• Created: 2021-01-24T16:47:16.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2023-02-15T11:08:05.000Z (almost 2 years ago)
• Last Synced: 2024-12-07T04:40:43.602Z (15 days ago)
• Topics: asic, hdl, verilog
• Language: Verilog
• Homepage: https://zerotoasiccourse.com
• Size: 49.8 KB
• Stars: 10
• Watchers: 3
• Forks: 8
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE

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README

        
# Frequency counter

This repository is a template for project 2.2 that takes you through:

* Building an edge detector

* Building a seven segment driver

* Counting edges

* State machines

# License

This repo is part of the [Zero to ASIC course](https://zerotoasiccourse.com) and licensed with [Apache 2](LICENSE).

# Resources

* Verilog cheatsheet: https://marceluda.github.io/rp_dummy/EEOF2018/Verilog_Cheat_Sheet.pdf

* Clock domain crossing: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

* Flip flops and metastability: https://www.youtube.com/watch?v=5PRuPVIjEcs

* VHDL resources: https://docs.google.com/document/d/1RAQWjmxpJndlEJdLWXK8irIqWuYTstqu7pU3tOIFccc/edit

* Charles Eric LaForest design elements guide: http://fpgacpu.ca/fpga/index.html