https://github.com/mattvenn/memrd-problem
https://github.com/mattvenn/memrd-problem
Last synced: about 2 months ago
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- Host: GitHub
- URL: https://github.com/mattvenn/memrd-problem
- Owner: mattvenn
- Created: 2017-11-17T18:08:07.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2017-11-24T08:57:41.000Z (over 7 years ago)
- Last Synced: 2025-04-01T18:09:54.657Z (about 2 months ago)
- Language: Verilog
- Size: 2.93 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# memrd example
I'm hoping someone can explain this behaviour to me.
I have a number of [ADCs generated with a genvar loop](top.v).
If I use an array of regs to register the data, then the LEDS never show the
data. (line 13).
If I use an array of wires to connect the LEDS to the ADC values, the LEDs
work. (line 12).
yosys show (try `make show`) shows with the array of registers, memrd blocks are created. I don't know what these do...