https://github.com/mattvenn/multi-project-harness

https://github.com/mattvenn/multi-project-harness

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/mattvenn/multi-project-harness
• Owner: mattvenn
• License: apache-2.0
• Created: 2020-11-11T12:18:23.000Z (over 4 years ago)
• Default Branch: main
• Last Pushed: 2021-02-04T13:42:52.000Z (over 4 years ago)
• Last Synced: 2025-04-01T18:09:54.817Z (about 2 months ago)
• Language: Verilog
• Size: 376 KB
• Stars: 4
• Watchers: 3
• Forks: 4
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Multi Project Harness

This is a proposal for handling multiple projects in the user project area of the [Caravel harness](https://github.com/efabless/caravel)

clone with --recursive to get the demo project [seven segment seconds](https://github.com/mattvenn/seven-segment-seconds)

You will also need cocotb and iverilog installed.

    install iverilog from source git://github.com/steveicarus/iverilog.git

    pip3 install cocotb

![multi project harness diagram](docs/multi-project-harness.png)

![multi project gds](docs/multi-project-gds.png)

# Process of adding a new design

## Context 1: add to multi-project-harness

* add design as a submodule

* add sources to includes.v

* add sources to Makefile for cocotb test

* add a test to the test_harness.py

* add blackbox module definition to blackbox.v

## Context 2: Caravel

* clone caravel and add this repo as a submodule in caravel/verilog/rtl

* add firmware and test in caravel/verilog/dv/caravel/user_proj_example

* run the test and check your design is selected and generating expected signals. Best if the testbench actually checks something basic.

* see https://github.com/mattvenn/caravel/tree/multi-project/verilog/dv/caravel/user_proj_example/seven-segment-counter for an example

## Context 3: OpenLane

Each design is hardened (turned into a GDS2 layout) and then aggrated into the top module. See here for more [info](docs/hardening.md)

# Simulation / Verification

run a simulation of activating one design and then the next:

    make sim

    make gtkwave

run a formal proof that the mux is correct

    make formal