https://github.com/mattvenn/seven_segment_seconds
Demo project for Zero to ASIC course & presentations
https://github.com/mattvenn/seven_segment_seconds
asic demo verilog
Last synced: about 2 months ago
JSON representation
Demo project for Zero to ASIC course & presentations
- Host: GitHub
- URL: https://github.com/mattvenn/seven_segment_seconds
- Owner: mattvenn
- License: apache-2.0
- Created: 2020-11-08T19:21:05.000Z (over 4 years ago)
- Default Branch: mpw7
- Last Pushed: 2022-07-27T14:55:16.000Z (almost 3 years ago)
- Last Synced: 2025-04-01T18:09:55.523Z (about 2 months ago)
- Topics: asic, demo, verilog
- Language: Verilog
- Homepage: https://zerotoasiccourse.com/
- Size: 18.6 KB
- Stars: 5
- Watchers: 2
- Forks: 1
- Open Issues: 0