https://github.com/mattvenn/seven_segment_seconds

Demo project for Zero to ASIC course & presentations
https://github.com/mattvenn/seven_segment_seconds

asic demo verilog

Last synced: 19 days ago
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Demo project for Zero to ASIC course & presentations

• Host: GitHub
• URL: https://github.com/mattvenn/seven_segment_seconds
• Owner: mattvenn
• License: apache-2.0
• Created: 2020-11-08T19:21:05.000Z (about 4 years ago)
• Default Branch: mpw7
• Last Pushed: 2022-07-27T14:55:16.000Z (over 2 years ago)
• Last Synced: 2023-03-16T20:15:50.925Z (over 1 year ago)
• Topics: asic, demo, verilog
• Language: Verilog
• Homepage: https://zerotoasiccourse.com/
• Size: 18.6 KB
• Stars: 4
• Watchers: 2
• Forks: 1
• Open Issues: 0

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