https://github.com/mattvenn/simple-arbiter
https://github.com/mattvenn/simple-arbiter
Last synced: about 2 months ago
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- Host: GitHub
- URL: https://github.com/mattvenn/simple-arbiter
- Owner: mattvenn
- Created: 2018-12-08T20:22:54.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2018-12-09T19:55:19.000Z (over 6 years ago)
- Last Synced: 2025-04-01T18:09:55.537Z (about 2 months ago)
- Language: Verilog
- Size: 17.6 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# FIFO arbiter
many modules want to store records to a FIFO. Instead of using 1 FIFO per module,
use an arbiter to grant FIFO write access.
## FIFO definition
just the data writing side
input [7:0] i_data, // data input
input i_we, // high to write the data to FIFO
## Writer module definition
output [7:0] o_data, // data to write
output o_req, // signal ready to write data
input i_busy, // arbiter busy
## Arbiter module definition
input [NUM_WRITERS*8-1:0] i_data, // incoming data bus
input [NUM_WRITERS-1:0] i_req // write request from Writer module
output [NUM_WRITERS-1:0] o_busy // busy line, Writer must keep data
output o_we, // write to FIFO
output [7:0] o_data // data out
# Questions
## bus sharing
tried to use a single 8 bit bus with writers setting output to z when not
granted access. This didn't work with yosys tristate stuff.
So made a i_data large enough for all o_data. But get this warning:
Warning: multiple conflicting drivers for arbiter.\i_data [1]:
Also, any way of parameterising the input into multiple ports instead of one
large bus?
Also, if bus can be set to zz, could I avoid channeling all writer's o_data into
i_data? And join all the o_data into 1 bus and then connect this direct to fifo.
## assumption/assume affects cover
writer.v asserts that it will behave correctly in terms of not dropping req
until !busy. arbiter.v assumes this behaviour. With both assumption and
assertion the cover never works.