https://github.com/mattvenn/wrapped_function_generator
https://github.com/mattvenn/wrapped_function_generator
Last synced: 2 months ago
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- Host: GitHub
- URL: https://github.com/mattvenn/wrapped_function_generator
- Owner: mattvenn
- License: apache-2.0
- Created: 2021-12-10T14:35:00.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-05-04T11:18:33.000Z (about 3 years ago)
- Last Synced: 2025-04-01T18:09:57.735Z (2 months ago)
- Language: Verilog
- Size: 9.39 MB
- Stars: 2
- Watchers: 2
- Forks: 1
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Function generator
Example project that uses the shared RAM as data for an arbitrary function generator.
The output is an 8bit port to a DAC.
In the function_generator directory:
* Run make to run the unit tests.
* Run make show_generator to see the waveform.
## Caravel Bus interface
Responds to reads and writes at the given BASE_ADDRESS (defaults to 0x3000_000)
DATA PARTITION NAME DESCRIPTION
15:0 period clock cycles between putting next data on the output
23:16 ram_end_addr where to start reading the data in the shared RAM
24 run if high, set the design running
## RAMBus interface
* At init, read the first word from RAM.
* Starts reading a 32 bit word at address 0 from the shared RAM.
* Every period cycles, update the DAC output.
* After the last 8 bit word is put on the DAC output, start a new wishbone request for the next 32 bits of data.
# Shared RAM
For more information about the shared RAM, [see this doc](https://docs.google.com/document/d/1wLjU6hkAoYvSWNBAyTj8HmIV70eJWU3apa9_OEpsd3Y/edit#)
# Dependencies
* cocotb
* cocotb bus extension for wishbone