https://github.com/mattvenn/wrapped_instrumented_adder

https://github.com/mattvenn/wrapped_instrumented_adder

Last synced: about 2 months ago
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• Host: GitHub
• URL: https://github.com/mattvenn/wrapped_instrumented_adder
• Owner: mattvenn
• License: apache-2.0
• Created: 2022-06-02T10:04:47.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-06-07T16:22:59.000Z (almost 3 years ago)
• Last Synced: 2025-04-01T18:09:57.740Z (about 2 months ago)
• Language: Verilog
• Size: 29.8 MB
• Stars: 4
• Watchers: 3
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Instrumented adder

Main [README is here](https://github.com/mattvenn/instrumented_adder).

# Zero to ASIC Course

This project was made as part of the [Zero to ASIC Course](https://zerotoasiccourse.com)!

# License

This project is [licensed under Apache 2](LICENSE)