https://github.com/max22-/rv32

RISC-V (32-bit) emulator, in C89
https://github.com/max22-/rv32

c89 emulator risc-v risc-v-emulator riscv simulator

Last synced: 3 months ago
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RISC-V (32-bit) emulator, in C89

• Host: GitHub
• URL: https://github.com/max22-/rv32
• Owner: max22-
• License: mit
• Created: 2022-07-13T21:09:02.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2024-07-13T22:59:46.000Z (6 months ago)
• Last Synced: 2024-09-30T01:22:02.621Z (3 months ago)
• Topics: c89, emulator, risc-v, risc-v-emulator, riscv, simulator
• Language: C
• Homepage:
• Size: 139 KB
• Stars: 2
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Credits / Links

## Learning

### Not Risc-v related, but very interesting to learn low level stuff

[Write your own virtual machine](https://www.jmeiners.com/lc3-vm/) \

[Uxn](https://wiki.xxiivv.com/site/uxn.html)

### Simulator

[RARS -- RISC-V Assembler and Runtime Simulator](https://github.com/TheThirdOne/rars)

## Other implementations

[https://github.com/cnlohr/mini-rv32ima/](https://github.com/cnlohr/mini-rv32ima/)

[https://github.com/racerxdl/riscv-emulator](https://github.com/racerxdl/riscv-emulator) \

[https://github.com/edubart/riscvm](https://github.com/edubart/riscvm)

## Testing

[picorv32](https://github.com/YosysHQ/picorv32) \

[About the Testing of My Simple RISC-V Core (regymm(Peter Gu)'s Blog)](https://www.ustcpetergu.com/MyBlog/experience/2021/07/09/about-riscv-testing.html)