https://github.com/maxxsoft/bossa
BOOM's Simulation Accelerator.
https://github.com/maxxsoft/bossa
accelerator boom chipyard chisel firrtl risc-v riscv rocket rocket-chip rtl simulation soc verilator
Last synced: about 2 months ago
JSON representation
BOOM's Simulation Accelerator.
- Host: GitHub
- URL: https://github.com/maxxsoft/bossa
- Owner: MaxXSoft
- License: gpl-3.0
- Created: 2021-11-29T03:05:53.000Z (over 3 years ago)
- Default Branch: master
- Last Pushed: 2021-12-16T04:06:04.000Z (over 3 years ago)
- Last Synced: 2025-03-29T14:41:27.940Z (2 months ago)
- Topics: accelerator, boom, chipyard, chisel, firrtl, risc-v, riscv, rocket, rocket-chip, rtl, simulation, soc, verilator
- Language: Scala
- Homepage:
- Size: 104 KB
- Stars: 13
- Watchers: 2
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE
Awesome Lists containing this project
README
# Boosa: BOOM's Simulation Accelerator
Bossa is a [Chipyard](https://github.com/ucb-bar/chipyard)-based framework designed to accelerate the BOOM simulation process.
Bossa keeps only the necessary components for simulating BOOM, and the submodules in Chipyard, such as Gemmini, Hwacha, IceNet, NVDLA, etc. are all removed.
Bossa will use [Frenda](https://github.com/MaxXSoft/Frenda) to incrementally compile the generated FIRRTL. This will be very helpful if you keep modifying the BOOM and then run simulation again and again, it can save you a lot of time.
Bossa currently supports only Verilator-based simulations.
## Prerequisites
### Using Bossa's Docker Image
Just run:
```sh
docker pull maxxing/bossa-image
docker run -it maxxing/bossa-image bash
```
See [docker/README.md](docker/README.md) for more details.
### Using Bossa on Your Local Machine
* Ubuntu (20.04+ recommended).
* JDK 11+.
* C++ compiler and Make (`build-essential`).
* Python 3.7+.
* Verilator.
* Device tree compiler (for building `riscv-isa-sim`).
* Git.
You can run the following command to setup prerequisites on Ubuntu:
```sh
sudo scripts/setup-prerequisites.sh
```
## Getting Started
### Setting Up Prerequisites and Initializing
```sh
sudo scripts/setup-prerequisites.sh
git submodule update --init --recursive --depth=1
```
### Building for Simulation
```sh
cd sims/verilator
# build simulation for small BOOM
make CONFIG=SmallBoomConfig -j`nproc`
# or, enable multi-threading
make CONFIG=SmallBoomConfig VERILATOR_THREADS=8 -j`nproc`
# or, enable debugging with VCD waveform dump
make CONFIG=SmallBoomConfig debug -j`nproc`
# or, enable debugging with FST waveform dump
make CONFIG=SmallBoomConfig VERILATOR_FST_MODE=1 debug -j`nproc`
```
### Bulding and Running Simulator
```sh
cd sims/verilator
make CONFIG=SmallBoomConfig -j`nproc`
./simulator-SmallBoomConfig path/to/riscv/program
```
## Make Options Supported during Simulator Build
* `CONFIG`: the configuration class to give the parameters for the project (default `SmallBoomConfig`).
* `FRENDA_THREADS`: how many threads the incremental FIRRTL compiler will use (default `nproc`).
* `FRENDA_CLEAN_BUILD`: perform clean FIRRTL build instead of incremental FIRRTL build.
* `VERILATOR_THREADS`: how many threads the simulator will use (default 1).
* `VERILATOR_FST_MODE`: enable FST waveform instead of VCD. use with debug build.
* `TOP_MODULE`: the top level module of the project (default `TestHarness`).
* `VERILATOR_OPT_FLAGS`: Verilator optimization flags (default `-O2 --x-assign fast --x-initial fast --output-split 30000 --output-split-cfuncs 30000`).
## Changelog
See [CHANGELOG.md](CHANGELOG.md).