https://github.com/mazegen/x86reference

X86 Opcode and Instruction Reference
https://github.com/mazegen/x86reference

assembler instruction-set opcode parsable reference x64 x86

Last synced: 3 months ago
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X86 Opcode and Instruction Reference

• Host: GitHub
• URL: https://github.com/mazegen/x86reference
• Owner: mazegen
• License: lgpl-3.0
• Created: 2024-06-05T14:15:39.000Z (7 months ago)
• Default Branch: master
• Last Pushed: 2024-06-10T13:31:38.000Z (7 months ago)
• Last Synced: 2024-09-30T05:45:29.451Z (3 months ago)
• Topics: assembler, instruction-set, opcode, parsable, reference, x64, x86
• Language: Python
• Homepage: https://ref.x86asm.net
• Size: 153 KB
• Stars: 5
• Watchers: 1
• Forks: 2
• Open Issues: 22
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# X86 Opcode and Instruction Reference

Work-in-progress repository. For more see [ref.x86asm.net](http://ref.x86asm.net).

### Notes on Addressing Methods

#### The `J` method

Might be confusing. For example, `Jbs` actually reads as: "Relative offset to be added to the IP register. The relative offset is sign-extended to the size of of the IP register."

This method is always used as a source operand. To make it completely correct, it should be a destination operand but it would make the byte value also the destination and that doesn't make much sense. This would need to be solved by introducing new types of operands but I don't think it's worth it.

### Notes on Operand Type codes

#### SIMD FP instructions with integer codes

There are several MOV-like SIMD instructions that operate on floating-point data but their operands are indicated as integer ones. For example [`MOVHLPS Vq, Uq`](http://ref.x86asm.net/geek.html#x0F12) means "Move two packed single precision floating-point values from high quadword of source XMM register to low quadword of destination XMM register", however, all the Intel manuals from the pre-AVX era doesn't indicate its operands as packed single FP values (`ps` code) in the opcode map. This is presumably because the operands are treated as integers during the move operation.

The newer manuals from the AVX era indicate this instruction as `VMOVHLPS Vq, Hq, Uq` in the opcode map, making it unclear how the non-AVX version should look like. Anyway, even the AVX version uses integer codes.