https://github.com/mcejp/poly94

Yet another faux-retro game system
https://github.com/mcejp/poly94

cocotb fpga prjtrellis ulx3s vexriscv yosys

Last synced: about 1 month ago
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Yet another faux-retro game system

• Host: GitHub
• URL: https://github.com/mcejp/poly94
• Owner: mcejp
• License: gpl-3.0
• Created: 2022-04-22T19:48:34.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2024-03-03T20:09:37.000Z (10 months ago)
• Last Synced: 2024-03-03T21:24:53.846Z (10 months ago)
• Topics: cocotb, fpga, prjtrellis, ulx3s, vexriscv, yosys
• Language: Verilog
• Homepage:
• Size: 1.48 MB
• Stars: 2
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# Poly94 computing platform

![snapshot](_img/snapshot.jpg)

![architecture](_img/poly94_architecture.png)

![Fmax badge](https://img.shields.io/endpoint?url=https%3A%2F%2Fmcejp.gitlab.io%2FPoly94%2Ffmax.json)

![Benchmark badge](https://img.shields.io/endpoint?url=https%3A%2F%2Fmcejp.gitlab.io%2FPoly94%2Fdmips.json)

## Connecting ULX3S

You need to connect to USB1 (US1) connector to the host computer in order to program the board.



## Development environment

Highly recommended to use the YosysHQ [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build). It includes all of the necessary tools (and many more):

- Yosys

- nextpnr-ecp5

- Verilator

- Icarus Verilog

- Python & cocotb

## Build and program bitstream

```

make ulx3s.bit    # (optional)

make prog

```

## Testing

```

# Verilator (currently not working with SDRAM model)

make sim

# Verilator with options

BOOTROM=firmware/build/test_framebuffer.bin DUMP_FRAMEBUF=framebuffer.ppm NUM_CYCLES=4000000 make sim

# cocotb

make -f Makefile.coco

```