https://github.com/mcleber/verilog_studies
This repository contains my studies and experiments with Verilog HDL.
https://github.com/mcleber/verilog_studies
amd-xilinx gowin gowin-eda learning-verilog tang-primer-20k verilog verilog-hdl vivado vivado-vitis xilinx xilinx-fpga xilinx-vivado
Last synced: 8 months ago
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This repository contains my studies and experiments with Verilog HDL.
- Host: GitHub
- URL: https://github.com/mcleber/verilog_studies
- Owner: mcleber
- License: gpl-3.0
- Created: 2025-01-05T06:22:34.000Z (10 months ago)
- Default Branch: main
- Last Pushed: 2025-02-27T05:53:48.000Z (8 months ago)
- Last Synced: 2025-02-27T06:35:45.084Z (8 months ago)
- Topics: amd-xilinx, gowin, gowin-eda, learning-verilog, tang-primer-20k, verilog, verilog-hdl, vivado, vivado-vitis, xilinx, xilinx-fpga, xilinx-vivado
- Language: Verilog
- Homepage:
- Size: 104 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE