https://github.com/mcleber/verilog_traffic_light

First steps with the Sipeed Tang Primer 20k FPGA.
https://github.com/mcleber/verilog_traffic_light

gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl

Last synced: 3 months ago
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First steps with the Sipeed Tang Primer 20k FPGA.

• Host: GitHub
• URL: https://github.com/mcleber/verilog_traffic_light
• Owner: mcleber
• License: gpl-3.0
• Created: 2025-03-05T00:33:11.000Z (3 months ago)
• Default Branch: main
• Last Pushed: 2025-03-05T01:05:47.000Z (3 months ago)
• Last Synced: 2025-03-05T01:28:51.819Z (3 months ago)
• Topics: gowin, gowin-eda, learning-verilog, sipeed, sipeed-tang-primer, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 0 Bytes
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Verilog Traffic Light

First steps with the Sipeed Tang Primer 20k FPGA.

The code for traffic light control was written in Verilog.