https://github.com/mcleber/verilog_traffic_light_controller
First steps with the Sipeed Tang Primer 20k FPGA.
https://github.com/mcleber/verilog_traffic_light_controller
gowin gowin-eda learning-verilog sipeed sipeed-tang-primer verilog verilog-hdl
Last synced: 3 months ago
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First steps with the Sipeed Tang Primer 20k FPGA.
- Host: GitHub
- URL: https://github.com/mcleber/verilog_traffic_light_controller
- Owner: mcleber
- License: gpl-3.0
- Created: 2025-03-05T00:33:11.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2026-03-04T02:08:49.000Z (4 months ago)
- Last Synced: 2026-03-04T05:54:52.349Z (4 months ago)
- Topics: gowin, gowin-eda, learning-verilog, sipeed, sipeed-tang-primer, verilog, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 1.76 MB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE