https://github.com/mcquerol/direct-digital-frequency-synthesis-systemverilog

SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.
https://github.com/mcquerol/direct-digital-frequency-synthesis-systemverilog

ddfs fpga lut pwm sine-wave systemverilog time-base-generation

Last synced: 7 months ago
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SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.

• Host: GitHub
• URL: https://github.com/mcquerol/direct-digital-frequency-synthesis-systemverilog
• Owner: mcquerol
• License: mit
• Created: 2024-08-14T01:31:29.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2024-12-18T01:21:56.000Z (10 months ago)
• Last Synced: 2025-01-04T15:34:45.193Z (9 months ago)
• Topics: ddfs, fpga, lut, pwm, sine-wave, systemverilog, time-base-generation
• Language: SystemVerilog
• Size: 509 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# direct-digital-frequency-synthesis-systemverilog