https://github.com/mediaic/vlsi_lab1

RTL + Synthesis + APR
https://github.com/mediaic/vlsi_lab1

Last synced: about 2 months ago
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RTL + Synthesis + APR

• Host: GitHub
• URL: https://github.com/mediaic/vlsi_lab1
• Owner: mediaic
• Created: 2018-07-02T08:58:35.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2023-08-01T14:35:23.000Z (over 1 year ago)
• Last Synced: 2023-08-01T15:53:10.203Z (over 1 year ago)
• Language: Verilog
• Size: 6.56 MB
• Stars: 10
• Watchers: 3
• Forks: 1
• Open Issues: 1

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