https://github.com/mediaic/vlsi_lab2

RTL + Verfication + Synthesis + APR
https://github.com/mediaic/vlsi_lab2

Last synced: about 2 months ago
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RTL + Verfication + Synthesis + APR

• Host: GitHub
• URL: https://github.com/mediaic/vlsi_lab2
• Owner: mediaic
• Created: 2018-07-02T09:04:24.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-07-18T10:56:32.000Z (over 6 years ago)
• Last Synced: 2023-03-06T20:34:59.691Z (almost 2 years ago)
• Language: SystemVerilog
• Size: 772 KB
• Stars: 8
• Watchers: 3
• Forks: 0
• Open Issues: 0

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