https://github.com/megaing/tc-to-verilog
Turing Complete circuit to verilog
https://github.com/megaing/tc-to-verilog
Last synced: about 1 year ago
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Turing Complete circuit to verilog
- Host: GitHub
- URL: https://github.com/megaing/tc-to-verilog
- Owner: MegaIng
- Created: 2022-04-26T23:25:58.000Z (about 4 years ago)
- Default Branch: master
- Last Pushed: 2022-05-17T08:36:52.000Z (about 4 years ago)
- Last Synced: 2025-03-27T06:22:28.998Z (about 1 year ago)
- Language: Python
- Size: 261 KB
- Stars: 10
- Watchers: 2
- Forks: 3
- Open Issues: 1
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Metadata Files: