https://github.com/memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
https://github.com/memgonzales/hdl-flip-flop
behavioral-modeling computer-architecture flip-flop sequential-circuits verilog
Last synced: 2 months ago
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Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
- Host: GitHub
- URL: https://github.com/memgonzales/hdl-flip-flop
- Owner: memgonzales
- Created: 2021-06-14T04:17:14.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2022-12-25T15:24:50.000Z (over 2 years ago)
- Last Synced: 2025-01-20T11:11:27.213Z (4 months ago)
- Topics: behavioral-modeling, computer-architecture, flip-flop, sequential-circuits, verilog
- Language: Verilog
- Homepage:
- Size: 102 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Behavioral Modeling of Flip-Flops
This project is a compilation of Verilog **behavioral models** and test benches for the four types of flip-flops:
- SR flip-flops
- JK flip-flops
- D flip-flops
- T flip-flops
Each of these is implemented as **positive edge-triggered, with inverted and non-inverted outputs, and asynchronous reset (active-high)**. *Positive edge-triggered* describes a flip-flop where changes in its state happen only at the rising edge (low-to-high transition) of the clock. Meanwhile, *asynchronous reset* indicates that the activation of the reset results in the state immediately changing to 0, regardless of the synchronous input/s or the clock.
## Overview of Flip-Flops
Mano (1992) defines a *flip-flop* — the data storage element of synchronous sequential circuits — as "a binary cell capable of storing one bit of information" (p. 22).
### SR Flip-Flop
*Characteristic Table*
*S* | *R* | *Q*(*t* + 1) | Remarks
-- | -- | -- | --
0 | 0 | *Q*(*t*) | No change
0 | 1 | 0 | Reset
1 | 0 | 1 | Set
1 | 1 | ? | Indeterminate
*Waveform*
### JK Flip-Flop
*Characteristic Table*
*J* | *K* | *Q*(*t* + 1) | Remarks
-- | -- | -- | --
0 | 0 | *Q*(*t*) | No change
0 | 1 | 0 | Reset
1 | 0 | 1 | Set
1 | 1 | ¬*Q*(*t*) | Toggle
*Waveform*
### D Flip-Flop
*Characteristic Table*
*D* | *Q*(*t* + 1) | Remarks
-- | -- | --
0 | 0 | Same as *D*
1 | 1 | Same as *D*
*Waveform*
### T Flip-Flop
*Characteristic Table*
*T* | *Q*(*t* + 1) | Remarks
-- | -- | --
0 | *Q*(*t*) | No change
1 | ¬*Q*(*t*) | Toggle
*Waveform*
*Note that the behavioral modeling of flip-flops is derived from their respective characteristic tables.*
## Built Using
This project consists of source codes and test benches written in the hardware description language **Verilog**.
If Icarus Verilog is installed, run the following command on the terminal to compile the Verilog program:
```
iverilog -o .vvp .v .v
```
To "execute" the program and generate the value change dumpfile (.vcd), run the following command:
```
vvp .vvp
```
To generate and view the waveform using GTKWave, run the following command:
```
gtkwave .vcd
```
In this project, the filenames (with extensions) are as follows:
Flip-Flop | Source Code | Test Bench | VCD File
--- | --- | --- | ---
**SR** | sr.v | sr_tb.v | sr.vcd
**JK** | jk.v | jk_tb.v | jk.vcd
**D** | d.v | d_tb.v | d.vcd
**T** | t.v | t_tb.v | t.vcd
## Author and References
- **Mark Edward M. Gonzales**
[email protected]
[email protected]
The following reference materials were consulted:
- Doering, E.R. (2002, October 4). *Gradual introduction to Verilog syntax: Basic sequential circuits*. Rose-Hulman Institute of Technology. https://www.rose-hulman.edu/class/ee/laflen/ece333/Resources/VerilogSequential.htm
- Mano, M.M. (1992). *Computer system architecture* (3rd ed.). Pearson.
- Uy, R.L. (2021). *CSARCH lecture series: Hardware description language for sequential circuit.* De La Salle University.