https://github.com/mengstr/vuart
WIP - Smallish UART written in Verilog
https://github.com/mengstr/vuart
uart uart-verilog verilog wip-do-not-use
Last synced: 10 months ago
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WIP - Smallish UART written in Verilog
- Host: GitHub
- URL: https://github.com/mengstr/vuart
- Owner: mengstr
- Created: 2020-02-06T09:33:03.000Z (almost 6 years ago)
- Default Branch: master
- Last Pushed: 2020-02-06T22:21:54.000Z (almost 6 years ago)
- Last Synced: 2023-03-11T04:30:04.515Z (almost 3 years ago)
- Topics: uart, uart-verilog, verilog, wip-do-not-use
- Language: Verilog
- Homepage:
- Size: 445 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0