https://github.com/meow-chip/MeowV64

A superscalar RISC-V CPU with out-of-order execution and multi-core support
https://github.com/meow-chip/MeowV64

Last synced: 3 months ago
JSON representation

A superscalar RISC-V CPU with out-of-order execution and multi-core support

• Host: GitHub
• URL: https://github.com/meow-chip/MeowV64
• Owner: meow-chip
• License: mit
• Created: 2019-12-23T02:34:14.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2022-02-17T11:48:59.000Z (almost 3 years ago)
• Last Synced: 2024-08-03T01:39:20.662Z (6 months ago)
• Language: Scala
• Size: 1.84 MB
• Stars: 54
• Watchers: 6
• Forks: 4
• Open Issues: 11
• Metadata Files:
  • Readme: README.md
  • License: LICENSE
  • Authors: AUTHORS

Awesome Lists containing this project

README

        
MeowV64

=======================

MeowV64 is a synthesizable and configurable superscalar RISC-V CPU with out-of-order execution, L1/L2 caches and multicore support. MeowV64 implements the RV64IMAFDCSU ISA.

## Authors

See `AUTHORS` file

## License

All code under this repository is released under the MIT license. See `LICENSE` file.