https://github.com/mgriebling/lola

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.
https://github.com/mgriebling/lola

circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth

Last synced: about 2 months ago
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A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

• Host: GitHub
• URL: https://github.com/mgriebling/lola
• Owner: mgriebling
• Created: 2015-10-02T21:01:04.000Z (about 9 years ago)
• Default Branch: master
• Last Pushed: 2024-10-25T01:45:41.000Z (2 months ago)
• Last Synced: 2024-10-26T14:36:03.925Z (2 months ago)
• Topics: circuit-compiler, digital-circuit-design, lola, simulator, swift, verilog, vhdl, wirth
• Language: Swift
• Homepage:
• Size: 227 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
A digital design compiler and simulator to produce and test designs based on a Lola circuit description. 

Invented by Niklaus Wirth (designer of Pascal and many other languages) Lola is similar to other high-level circuit design languages like VHDL and Verilog except much simpler to learn and use.

For example, here's the design of a 4-bit binary counter:

```

MODULE Counter0 (IN clk: BIT; OUT d: [4] BIT);

  REG (clk) R: [4] BIT;

BEGIN

  R := {R.3 ^ R.3 & R.2 & R.1 & R.0, (* R.3 *)

        R.2 ^ R.2 & R.1 & R.0,       (* R.2 *)

        R.1 ^ R.1 & R.0,             (* R.1 *)

        ~R.0};                       (* R.0 *)

  d := R

END Counter0.

```