https://github.com/michaeljclark/riscv-meta

RISC-V Instruction Set Metadata
https://github.com/michaeljclark/riscv-meta

metadata risc risc-v riscv

Last synced: about 2 months ago
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RISC-V Instruction Set Metadata

• Host: GitHub
• URL: https://github.com/michaeljclark/riscv-meta
• Owner: michaeljclark
• License: other
• Created: 2017-11-15T02:23:51.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2018-10-21T23:46:48.000Z (over 6 years ago)
• Last Synced: 2024-11-05T21:26:19.531Z (3 months ago)
• Topics: metadata, risc, risc-v, riscv
• Homepage:
• Size: 39.1 KB
• Stars: 39
• Watchers: 5
• Forks: 11
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# RISC-V Metadata

This directory contains metadata for the RISC-V Instruction Set

|File|Description|

|:---|:----------|

|`codecs`               |Instruction encodings|

|`compression`          |Compressed instruction|

|`constraints`          |Constraint definitions|

|`csrs`                 |Control and status registers|

|`csr-fields`           |Control and status register fields|

|`enums`                |Enumerated types|

|`extensions`           |Instruction set extensions|

|`formats`              |Disassembly formats|

|`opcodes`              |Opcode encoding information|

|`opcode-classes`       |Instruction classes|

|`opcode-descriptions`  |Instruction descriptions|

|`opcode-fullnames`     |Instruction full names|

|`opcode-majors`        |Major opcodes|

|`opcode-pseudocode-c`  |Instruction pseudo code (C)|

|`opcode-pseudocode-alt`|Instruction pseudo code (Alternative)|

|`operands`             |Operand bit encodings|

|`pseudos`              |Pseudo instructions|

|`registers`            |Registers ABI definitions|

|`types`                |Instruction types|

riscv-meta is derived from [riscv-opcodes](https://github.com/riscv/riscv-opcodes)