https://github.com/mithro/pciee
Experiments in understanding PCIe topology of my Supermicro servers....
https://github.com/mithro/pciee
Last synced: 4 months ago
JSON representation
Experiments in understanding PCIe topology of my Supermicro servers....
- Host: GitHub
- URL: https://github.com/mithro/pciee
- Owner: mithro
- License: apache-2.0
- Created: 2023-05-03T20:04:55.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2023-05-27T20:28:08.000Z (about 3 years ago)
- Last Synced: 2026-02-05T14:48:42.430Z (4 months ago)
- Language: Roff
- Size: 1.32 MB
- Stars: 6
- Watchers: 4
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
Experiments in understanding PCIe
"Chassis" (case with motherboard, etc) I currently have;
* Supermicro SuperServer 4028GR-TVRT
* Supermicro SuperStorage SSG-6049P-E1CR60L
* IBM AC922 8335-GTH
* Dell PowerEdge C410x
The Supermicro 4028GR-TVRT has 2 x `PEX 9765` (65 lane, 17 port, PCI Express Gen3 ExpressFabric Platform) switches in it.
The Dell C410X has 4 x `PEX 8696` (96-Lane, 24-Port PCI Express Gen 2 - 5.0 GT/s) switches in it.
The IBM AC922 8335-GTH has a `PEX 8733` (32-Lane, 18-Port PCI Express Gen 3 - 8 GT/s) switch in it.
I also have the following "expansion cards";
* Supermicro `AOC-SLG3-8E2P` which has a Microsemi / SwitchTec `PM8562` (Switchtec PFX-L Fanout 32xG3 PCIe Switch) on it.
* Linkreal `LRNV9349-8I` which has a `PEX 8749` (48-Lane, 18-Port PCI Express Gen 3 - 8 GT/s) switch on it.
* One Stop Solutions `OSS-PCIE-HIB38-X16` which has a `PEX 8733` (32-Lane, 18-Port PCI Express Gen 3 - 8 GT/s) switch in it.
* Bunch of Qnap combined GigE / M.2 NVMe hardware.
I try to track this stuff in a [Google PCIe Switches Spreadsheet](https://docs.google.com/spreadsheets/d/1jZSAkNcLNtgT6uFQ9R1RPruqZ5_6tXa-Wqumv7s1jpU/edit#gid=1524818223) which should be publicly accessible.
Interesting PCIe Kernel Parameters - https://static.lwn.net/kerneldoc/admin-guide/kernel-parameters.html
* `pci=realloc` - Enable/disable reallocating PCI bridge resources if allocations done by BIOS are too small to accommodate resources required by all child devices.
* `pci=nocrs` - [X86] Ignore PCI host bridge windows from ACPI. If you need to use this, please report a bug.
* `pci=assign-busses` - [X86] Always assign all PCI bus numbers ourselves, overriding.
* `pci=pcie_scan_all` - Scan all possible PCIe devices. Otherwise we only look for one device below a PCIe downstream port.
* `pci=earlydump` - dump PCI config space before the kernel changes anything.