https://github.com/mithro/soft-utmi
A "soft" (VHDL) implementation of the UTMI+ PHYs specification using the SERDES found in Xilinx Spartan-6.
https://github.com/mithro/soft-utmi
Last synced: 5 months ago
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A "soft" (VHDL) implementation of the UTMI+ PHYs specification using the SERDES found in Xilinx Spartan-6.
- Host: GitHub
- URL: https://github.com/mithro/soft-utmi
- Owner: mithro
- License: apache-2.0
- Created: 2014-11-04T08:51:48.000Z (over 11 years ago)
- Default Branch: master
- Last Pushed: 2014-11-04T08:58:31.000Z (over 11 years ago)
- Last Synced: 2025-03-18T05:54:54.519Z (about 1 year ago)
- Language: VHDL
- Size: 1.89 MB
- Stars: 9
- Watchers: 4
- Forks: 5
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
soft-utmi
=========
A "soft" (VHDL) implementation of the UTMI+ PHYs specification using the SERDES
found in Xilinx Spartan-6.
The idea is to allow USB **2.0** to be run directly into the I/O pins of a
Xilinx Spartan-6. The Xilinx Spartan-6 isn't designed to do this, so it
requires a bunch of clever hacks to make work.
Once UTMI+ PHYs works, it should be able to be combined with the [daisho USB
core](https://github.com/mossmann/daisho/tree/master/sw/fpga/common/usb3).
Note, this would **only be USB2.0 support**, not USB3.0.
**This implementation does not work yet.**