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https://github.com/mpardalos/vera
Verified Verilog Equivalence checker, written and verified in Coq.
https://github.com/mpardalos/vera
Last synced: about 1 month ago
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Verified Verilog Equivalence checker, written and verified in Coq.
- Host: GitHub
- URL: https://github.com/mpardalos/vera
- Owner: mpardalos
- Created: 2024-02-09T10:05:16.000Z (11 months ago)
- Default Branch: master
- Last Pushed: 2024-11-22T19:09:33.000Z (about 1 month ago)
- Last Synced: 2024-11-22T20:19:40.715Z (about 1 month ago)
- Language: Coq
- Homepage:
- Size: 211 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: