https://github.com/mpatil/sv-embed-json

Embed JSON in SystemVerilog
https://github.com/mpatil/sv-embed-json

Last synced: 2 months ago
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Embed JSON in SystemVerilog

• Host: GitHub
• URL: https://github.com/mpatil/sv-embed-json
• Owner: mpatil
• License: mit
• Created: 2024-11-22T11:31:19.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2025-01-16T06:52:04.000Z (5 months ago)
• Last Synced: 2025-02-02T17:51:34.573Z (4 months ago)
• Language: SystemVerilog
• Size: 67.4 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
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# sv-embed-json

Yet another lib for embedding JSON in SystemVerilog. What's different is that this lib is extensible and the parser is generated from sv bnfc.

## Introduction

A string or a file with json formatted data can be read into a systemverilog class (`Val_`) representing the json value.

## Reference

1. [JSON Schema](https://www.json.org/json-en.html)

## Requirements

1. fusesoc

1. eda simulator -- only questa is tested right now.

## Development

1. Clone the repository: `git clone https://github.com/mpatil/sv-embed-json.git && cd sv-embed-json`

4. Setup simulator env. Only mentor questa supported right now.

5. Run the default test: `make -C src`