https://github.com/mplewis/verilive-server

Compile and execute Verilog modules and testbenches online. Built for Verilog.me.
https://github.com/mplewis/verilive-server

Last synced: 2 months ago
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Compile and execute Verilog modules and testbenches online. Built for Verilog.me.

• Host: GitHub
• URL: https://github.com/mplewis/verilive-server
• Owner: mplewis
• License: mit
• Created: 2014-07-23T08:01:34.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2022-06-27T16:11:27.000Z (over 2 years ago)
• Last Synced: 2024-04-13T04:56:10.163Z (10 months ago)
• Language: Python
• Size: 6.01 MB
• Stars: 2
• Watchers: 4
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# Verilive Server

Compile and execute Verilog modules and testbenches online. Built for [Verilog.me](http://www.verilog.me/).