https://github.com/mr-bossman/kisc-v

KISCV, a KISS principle riscv32i CPU
https://github.com/mr-bossman/kisc-v

cpu hdl risc-v riscv riscv32 verilog

Last synced: about 2 months ago
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KISCV, a KISS principle riscv32i CPU

• Host: GitHub
• URL: https://github.com/mr-bossman/kisc-v
• Owner: Mr-Bossman
• Created: 2023-01-17T14:21:18.000Z (about 2 years ago)
• Default Branch: master
• Last Pushed: 2024-08-16T04:35:40.000Z (6 months ago)
• Last Synced: 2024-10-30T12:12:09.930Z (3 months ago)
• Topics: cpu, hdl, risc-v, riscv, riscv32, verilog
• Language: Verilog
• Homepage:
• Size: 1.35 MB
• Stars: 20
• Watchers: 4
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Super simple microcodedd RISCV32I cpu.

 - 3(LUI/AUIPC/JAL), 4(ALU/BRANCH/JALR), 6(STORE/LOAD) clocks cycles per instrution.

 - No fence or CSR instructions (emulated with system rom)

 - No MMU.

 - Uses APB bus.

 - Runs Linux

 - Uses Verilator

## To try out yourself

 - Download and compile the latest Verilator

 - Download and compile the lastest Binutils and gcc

```bash

git submodule update --init --recursive

./dl_toolchain.sh

make CROSS_COMPILE=riscv32-unknown-elf- run_tests

make CROSS_COMPILE=riscv32-unknown-elf- testkern

```

## TODOS

 - Get running of actual FPGA

## Notes

### Tested on

 - GNU Binutils: 2.40.0.20230214

 - riscv32-unknown-elf-gcc (g2ee5e430018) 12.2.0

 - Verilator v5.012

Used precompiled:

https://github.com/riscv-collab/riscv-gnu-toolchain/releases/tag/2023.06.09

riscv32-elf-ubuntu-22.04-nightly-2023.06.09-nightly.tar.gz

Verilator has a few bugs in older verisons so you can't run `make VFLAGS='--assert'`

### Older version of binutils:

objcopy doesnt work when using `--verilog-data-width=4 --reverse-bytes=4` when converting from

elf to verilog mem files.

To get around this we first copy to raw binary then use the folowing to convert to verilog memfile.

`objcopy -Ibinary -O verilog --verilog-data-width=4 --reverse-bytes=4 test.bin test.mem`